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riscv
Riscv Isa Sim
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plic_uart_v1
merged
68aeeb55
·
Merge branch 'master' into plic_uart_v1
·
Oct 18, 2022
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increase-stack-size
4b0e9c16
·
Substantially increase context_t stack size
·
Sep 02, 2022
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debug_rom_fence
9e042c7b
·
Move fence inside entry_loop.
·
Jul 31, 2022
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trigger_priority
60ac4597
·
Simplify misaligned_load()
·
Jun 04, 2022
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simplify-misaligned
40cc0837
·
Actually inline load_fast/store_fast for clang/ARM
·
May 26, 2022
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factor-out-macros
merged
615de147
·
Factor out P extension macros into their own header
·
May 06, 2022
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test
merged
13ce3cb1
·
Enable precompiled headers when using clang
·
Jul 30, 2021
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p-ext-0.5.2
deb2cfe9
·
Merge pull request #694 from marcfedorow/p-ext
·
Apr 16, 2021
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sparse-mem
c234f51c
·
Add int_map and use it to speed up sparse mem
·
Feb 04, 2021
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load_reservation_set_size
d123f1e0
·
add configurable LR/SC reservation set
·
Aug 01, 2020
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heterogeneous_mc
7b9f7c55
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test_hetero_mc
·
Jul 31, 2020
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private-l1-caches
62412397
·
Make L1 cache models private caches
·
Jun 08, 2020
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sodor
90a04da3
·
fesvr: decrease DTM idle cycles
·
Dec 07, 2019
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pte-info-and-delegation
1536d430
·
Allow delegating misaligned load/store, illegal instruction
·
Nov 22, 2019
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static-link
merged
f49618ca
·
Add fesvr; only globally install fesvr headers/libs
·
Mar 31, 2019
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debug_rom
9a2904a9
·
Clean up/optimize Debug ROM.
·
Mar 05, 2019
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tweak_debug_rom
cc6a9c97
·
Debug ROM: Adjust debug ROM to have fewer icache flushes
·
May 01, 2018
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cycleh
74554e7d
·
Implement cycleh/instreth CSRs for RV32
·
Feb 13, 2018
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no_progbuf2
8b1cca83
·
Passes smoke tests with --progsize=0
·
Feb 02, 2018
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no_progbuf
2ccca5c1
·
Passes smoke tests with --progsize=0
·
Feb 01, 2018
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