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riscv
Riscv Isa Sim
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load_reservation_set_size
d123f1e0
·
add configurable LR/SC reservation set
·
Aug 01, 2020
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sparse-mem
c234f51c
·
Add int_map and use it to speed up sparse mem
·
Feb 04, 2021
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p-ext-0.5.2
deb2cfe9
·
Merge pull request #694 from marcfedorow/p-ext
·
Apr 16, 2021
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test
merged
13ce3cb1
·
Enable precompiled headers when using clang
·
Jul 30, 2021
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factor-out-macros
merged
615de147
·
Factor out P extension macros into their own header
·
May 06, 2022
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simplify-misaligned
40cc0837
·
Actually inline load_fast/store_fast for clang/ARM
·
May 26, 2022
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trigger_priority
60ac4597
·
Simplify misaligned_load()
·
Jun 04, 2022
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debug_rom_fence
9e042c7b
·
Move fence inside entry_loop.
·
Jul 31, 2022
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increase-stack-size
4b0e9c16
·
Substantially increase context_t stack size
·
Sep 02, 2022
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plic_uart_v1
merged
68aeeb55
·
Merge branch 'master' into plic_uart_v1
·
Oct 18, 2022
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itrigger-etrigger-cleanup
388753f9
·
Use ACTION_DEBUG_MODE instead of 1
·
Nov 16, 2022
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tmp
2cb5cf5d
·
For NS16550 UART, poll stdin less often
·
Jan 12, 2023
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speedup-hacks
4efafebe
·
tmp
·
Jan 12, 2023
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plctlab-plct-zce-fix2
c790cfd3
·
Contain C/Zc*-enable logic entirely within misa_csr_t
·
Feb 05, 2023
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plic-clint-endian
456c9e19
·
Make clint tolerant of discontiguous hart IDs
·
Feb 06, 2023
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rva-profile-support
54dd9179
·
WIP
·
Mar 31, 2023
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fix-bf16
84e2dca8
·
Add f64_to_bf16; fix f32_to_bf16
·
Apr 20, 2023
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rivosinc-etrigger_fix_exception_match
0e83fe66
·
Call stash_privilege more selectively
·
May 19, 2023
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whole-archive
3f7cfa8a
·
build: Link spike binaries with --whole-archive
·
Jul 10, 2023
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dynamic
2beafe8a
·
build: Dynamically link installed progs
·
Jul 10, 2023
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